Titre du projet: FAMOUS – Flot de modélisation et de conception rapide pour les systèmes dynamiquement reconfigurables

Résumé La reconfiguration dynamique est un moyen efficace pour rendre les systèmes flexibles et adaptables à une classe d'applications. Cependant, sa prise en compte à partir d'un haut niveau d'abstraction jusqu'à l'implémentation, n'est pas supportée par les outils de conception actuels. Le projet proposé vise à présenter une méthodologie complète qui prend en compte la reconfiguration dynamique du matériel, et propose les mécanismes nécessaires pour exploiter entièrement ces possibilités pendant l'exécution. Famous s'intéresse aux modèles de très haut niveau (UML), méthodes de compilation et d'exécution ainsi que les techniques d'analyse et de vérification. L'objectif est de fournir des outils pour une conception de qualité, améliorants la productivité, tout en garantissant l'optimisation des ressources matérielles utilisées et en réduisant le temps de mise sur le marché.

Partenaires:

INIRIA Lille - Nord Europe

Lab-STICC, Lorient

INRIA Rhône Alpes, Grenoble

Université de Bourgogne, Dijon

SODIUS

Coordinateur:

Samy Meftali – INRIA Lille Nord Europe

samy.meftali@lifl.fr

Financement ANR: 980 873 k€

Début :01/12/2009 - 48 mois

Référence: ANR-09-SEGI-003

Label: Image et réseaux

On Monday, November 23, Calin Glitia successfully defended his PhD, entitled "Optimisation des applications de traitement systématique intensives sur system-on-chip". You can download the manuscript (in French) and the slides (in English).

Abstract. Intensive signal processing applications appear in many application domains such as video processing or detection systems. These applications handle multidimensional data structures (mainly arrays) to deal with the various dimensions of the data (space, time, frequency). A specification language allowing the direct manipulation of these different dimensions with a high level of abstraction is a key to handling the complexity of these applications and to benefit from their massive
potential parallelism. The Array-OL specification language is designed to do just that.

In this thesis, we introduce an extension of Array-OL to express cycle dependences by the way of uniform inter-repetition dependences. We show that this specification language is able to express the main patterns of computation of the intensive signal processing domain. We discuss also the repetitive modeling of parallel applications, repetitive architectures and uniform mappings of the former to the latter, using the Array-OL concepts integrated into the Modeling and Analysis of Real-time and Embedded systems (MARTE) UML profile.

High-level data-parallel transformations are available to adapt the application to the execution, allowing to choose the granularity of the flows and a simple expression of the  mapping by tagging each repetition by its execution mode : data-parallel or sequential. The whole set of transformations was reviewed, extended and implemented as a
part of the Gaspard2 co-design environment for embedded systems.

With the introduction of the uniform dependences into the specification, our interest turns also on the interaction between these dependences and the high-level transformations. This is essential in order to enable the usage of the refactoring tools on the models with uniform dependences.

Based on the high-level refactoring tools, strategies and heuristics can be designed to help explore the design space. We propose a strategy that allows to find good trade-offs in the usage of storage and computation resources, and in the parallelism (both task and data parallelism) exploitation, strategy illustrated on an industrial radar application.

Two members of the team (Pierre Boulet and Calin Glitia) are in Sophia-Antipolis for the FDL and DASIP conferences. Pierre is the program chair of the UMES thematic area of FDL and Calin will present two papers (Interaction Between Inter-repetition Dependences and High Level Transformations by Calin Glitia, Pierre Boulet, and Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs by Imran-Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser) on Wednesday at DASIP.

Pierre also organized the second MARTE Users' Group meeting this morning. If you want to participate to this group, please send an email to Pierre.Boulet@lifl.fr. We are currently setting up a mailing list and a web page for the MUG. Check this page later for updates on this subject.

The DaRT project contributes to the improvement of the productivity of the electronic embedded system design teams. We structure our approach around a few key ideas:

• Promote the use of parallelism to help reduce the power consumption while improving the performance.
• Use of MDE (Model Driven Engineering) By separating the concerns in different models allowing reuse of these models and to keep them human readable.
• Propose an environment starting at the highest level of abstraction, namely the system modeling level.
• Automate code production by the use of (semi)-automatic model transformations to build correct by construction code.
• Develop simulation techniques at precise abstraction levels (functional, transactional or register transfer levels) to check the design the soonest.
• Prototype the resulting embedded systems of FPGA
• Promote strong semantics in the application model to allow verification, non ambiguous design and automatic code generation.
• Focus on a limited application domain, intensive signal processing applications. This restriction allows us to push our developments further without having to deal with the wide variety of applications.