2nd Workshop on:

Rapid Simulation and Performance Evaluation: Methods and Tools


January 24 (Sunday) 2010


Held in conjunction with

the 5th International Conference on High-Performance and

Embedded Architectures and Compilers (HiPEAC)

Pisa, Italy, January 25-28, 2010

Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).

The design space is huge though:

  1. How many cores do we need?

  2. Should we have a homogeneous or a heterogeneous design?

  3. When dynamic reconfiguration must be realized?

  4. How many caches/memories do we need?

  5. How to choose the instruction set(s) for these cores?

  6. What are the best code optimizations for a given application?

  7. How to combine the different metrics (e.g. energy, latency and throughput) into a global search space?


All these design questions lead to a huge design space that needs to be explored and which poses a grand challenge to search this space and to deliver an optimal design within the tight time-to-market budget.

In the embedded domain, the Intellectual Property (IP) based design approach is one of the most popular solutions to overcome this design challenge by relying on parameterized, pre-designed and pre-verified IP cores. Simulators are then used to explore the huge design space of interconnected IP cores for finding the optimal design for a given application domain.

In the general-purpose computing domain, the time-to-market is typically longer, the design is typically not limited to interconnecting pre-existing IP cores, however, the design should be optimized for a broader set of applications.

In both the embedded and the general-purpose domains, searching the huge design space during the design process is done through Design Space Exploration (DSE). DSE involves a number of key technologies such as modeling, simulation, prototyping, heuristic searching, etc. which have to cooperate in order to make the exploration effective, i.e., to obtain a final design with an optimal performance/power/cost/reliability ratio for the application domain of interest without compromising the time-to-market.

Although DSE is essential to both embedded and general-purpose processor design, both communities are largely unaware of each other’s work and progress. The purpose of this workshop therefore is to bridge this gap, and bring together researchers and practitioners from both communities to learn and discuss recent progress, and stimulate the interaction between both communities by exchanging ideas and sharing experiences. The workshop should provide a forum for brainstorming and road-mapping future DSE technologies for both the embedded and general-purpose domains.

Topics of interest include, but are not limited to:

·Rapid simulation techniques: sampled simulation, statistical simulation, hardware-accelerated simulation (e.g., using FPGAs), fast full-system simulation, parallel and distributed simulation, etc.

· High-level abstraction modeling, e.g., Transactional Level Modeling (TLM)

· Modeling and simulation techniques tailored towards multi-core and many-core architectures and/or embedded MPSoCs

·Rapid simulation techniques and design space exploration (DSE) for heterogeneous and dynamically reconfigurable systems.

· Dynamic binary translation for fast simulation, performance estimation and DSE

· Experience reports using existing simulators

· Simulator validation

Important dates

  1. Submission deadline: Nov 2, 2009 Nov 9 2009

  2. Notification to authors: Dec 15, 2009

  3. Final version of accepted papers: Dec 28, 2009

Paper submission & Registration

  1. The workshop will consist of invited talks by prominent academics and professionals, in conjunction with short presentation of works in progress. We expect to attract people from both academia and industry. Within HiPEAC, we look forward to to attract contributors and attendees from two research clusters, namely the “Simulation platform” and “Design methodology and tools” clusters.

  2. Submitted papers should use the LNCS format and should be 6 pages maximum. Manuscript preparation guidelines can be found at the LNCS specification web site (go to -> For Authors -> Information for LNCS Authors). Submissions must be sent to Smail.Niar[at]inria.fr.

  3. Accepted papers will be made available on the workshop web site.

  4. Information about registration, travel and hotels are available on the Hipeac conf web site: