PROGRAM (slides&papers) new-turning.gif

1st Workshop on

Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO’09)

January 25 (Sunday) 2009


Held in conjunction with
the 4th International Conference on High-Performance and
Embedded Architectures and Compilers (HiPEAC)
Paphos, Cyprus, January 25-28, 2009



Future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).
In the embedded systems domain, the Intellectual Property (IP) based design approach is one of the most popular solutions to overcome this design challenge by relying on parameterized and pre-designed IP cores. In the general-purpose computing domain, the time-to-market is typically longer, the design is typically not limited to interconnecting pre-existing IP cores, however, the design should be optimized for a broader set of applications. In both the embedded and the general-purpose domains, searching the huge design space during the design process is done through Design Space Exploration (DSE). DSE involves a number of key technologies such as modeling, simulation, prototyping, heuristic searching, etc. which have to cooperate in order to obtain a final design with an optimal performance/power/cost/reliability without compromising the time-to-market.

The purpose of this workshop is to look deeper into these issues, and bring researchers and practitioners from both communities (embedded systems and general purpose computing) together to explore and discuss recent progress, and stimulate the interaction between them through exchange of ideas and experience sharing. In the first part of the workshop, in-depth technology challenges and state-of-the-art research presentations will be given by key R&D actors from academia and industry. In the second part, selected research papers will be presented.

Topics of interest include, but are not limited to:

·           Rapid simulation techniques: sampled simulation, statistical simulation, hardware-accelerated simulation (e.g., using FPGAs), fast full-system simulation, parallel and distributed simulation, etc.

·           High-level abstraction modeling, e.g., Transactional Level Modeling (TLM)

·           Analytical modeling

·           Modeling and simulation techniques tailored towards multi-core and many-core architectures and/or MPSoCs

·           Multi-program and multi-threaded workload generation and simulation

·           Smart exploration techniques and (meta)heuristics for DSE

·           Industrial tools for rapid system design and analysis

·           Experience reports using existing simulators

·           Simulator validation

·           Simulation and modeling techniques for multi-layer software (including OSes, virtual machines, middleware and applications) running on future hardware



Smail Niar

INRIA Lille, France


Rainer Leupers

Aachen University, Germany


Olivier Temam

INRIA Orsay, France




Important dates

Submission deadline:

Nov 3, 2008, Nov 10, 2008

Notification to authors:

Nov 28, 2008

Final version of accepted papers:

Dec 19, 2008



Invited Speakers:

Norbert Wehn (TU Kaiserslautern, Germany): Simulation and Validation Challenges in Wireless Baseband Processing, Abstract.

Andrei Terechko (NXP Eindhoven, the Netherlands): Performance Density Exploration of Heterogeneous Multicore Architectures,  Abstract

Giovanni Beltrame (European Space Agency, the Netherlands): Know Before You Go: The Rise of System Level Simulation, Abstract

Babak Falsafi (EPFL, Lausanne, Switzerland): SimFlex & ProtoFlex, Full-System Emulators/Simulators for Large-Scale Multiprocessors,              Abstract

Nigel Topham (Institute for Computing Systems Architecture, University of Edinburgh, UK): Architecture Exploration through Ultra-Fast Simulation,      Abstract




List of accepted papers:

1.    Fast and Accurate Simulation Using the LLVM Compiler Framework, F. Brandner, A. Fellnhofer, A.S. Krall, and D.Riegler

2.   Integration of Power Saving Techniques in the UNISIM Simulation Framework Through the Shadow Module Design Paradigm,                                   D. Ludovici,  G. Keramidas, G.N. Gaydadjiev and S. Kaxiras

3.   Rapid Transactional Level Simulation for Multiprocessor Systems, I. Assayad and S. Yovine

4.    A DoE/RSM-based Strategy for an Efficient Design Space Exploration Targeted to CMPs, G. Palermo, C. Silvano, and  V. Zaccaria

5.   Improving Cycle-level Modular Simulation by Vectorization, D. Parello, M. Bouache, and B. Goossens

6.    System-level Modelling for SpiNNaker CMP System, M.M. Khan, E. Painkras, X. Jin, L.A. Plana, J.V. Woods and S.B. Furber

7.    System Level Performance Simulation for Heterogenous Multi-Processor Architectures, M. Streubühr, C. Haubelt, and J. Teich




Information about registration, travel and hotels are available on the Hipeac conf web site: