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West Team --- Publications

Publications

Most of the West Team recent publications are available here online. You can browse the abstracts.

Previous publications are also available.

The bibliography was generated with a custom version of the bib2xhtml package.

Bibliography

[1]

Christian Brunette, Jean-Pierre Talpin, Abdoulaye Gamatié, and Thierry Gautier. A metamodel for the design of polychronous systems. In Journal of Logic and Algebraic Programming - JLAP, Special Issue on Applying Concurrency Research to Industry, 2009. (To appear).

[2]

Sébastien Le Beux and Philippe Marquet and Jean-Luc Dekeyser. A design space exploration flow for fpga implementation of intensive signal processing applications. In Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Bruxelles, Belgium, November 2008.

[3]

Mouna Baklouti, Philippe Marquet, Muhammad Abid, and Jean-Luc Dekeyser. A design and an implementation of a parallel based simd architecture for soc on fpga. In Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Bruxelles, Belgium, November 2008.

[4]

Éric Piel, Philippe Marquet, and Jean-Luc Dekeyser. Model transformations for the compilation of multi-processor Systems-on-Chip. Generative and Transformational Techniques in Software Engineering II, 5235/2008:459–473, October 2008. (doi:10.1007/978-3-540-88643-3_13)

[5]

Sébastien Le Beux, Philippe Marquet, and Jean-Luc Dekeyser. Model driven engineering benefits for high level synthesis. Research Report 6615, INRIA, 2008.

[6]

César Olavo De Moura Filho, Anne Etien, Julien Taillard, Cédric Dumoulin, and Frédéric Guyomarc'H. Component-based models going generic : the marte case-study. Research Report 6632, INRIA, 2008.

[7]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, and Jean-Luc Dekeyser. Safe design of high-performance embedded systems in an mde framework. Innovations in Systems and Software Engineering (ISSE), 4(3), 2008.

[8]

Imran Rafiq Quadri, Samy Meftali, and Jean-Luc Dekeyser. MARTE based modeling approach for partial dynamic reconfigurable fpgas. In Sixth IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia 2008), Atlanta, USA, October 2008.

[9]

Huafeng Yu, Abdoulaye Gamatié, Eric Rutten, and Jean-Luc Dekeyser. Safe design of high-performance embedded systems in a MDE framework. In First IEEE International workshop UML and Formal Methods (UML&FM'08), Kitakyushu, Japan, October 2008. (To appear).

[10]

Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Anne Etien, Rabie Ben Atitallah, Philippe Marquet, and Jean-Luc Dekeyser. A model driven design framework for high performance embedded systems. Research Report 6614, INRIA, August 2008.

[11]

Abdoulaye Gamatié, Éric Rutten, and Huafeng Yu. A model for the mixed-design of data-intensive and control-oriented embedded systems. Research Report 6589, INRIA, France, July 2008.

[12]

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP Journal on Embedded Systems, 2008. (To appear).

[13]

Adolf Abdallah, Abdoulaye Gamatié, and Jean-Luc Dekeyser. MARTE-based Design of a Multimedia Application and Formal Analysis. In Forum on specification and design languages (FDL'08), Stuttgart, Germany, September 2008. (To appear).

[14]

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, and Jean-Luc Dekeyser. Modeling and Formal Validation of High-Performance Embedded Systems. In 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), Krakow, Poland, July 2008.

[15]

Calin Glitia and Pierre Boulet. High Level Loop Transformations for Multidimensional Signal Processing Embedded Applications. In International Symposium on Systems, Architectures, MOdeling, and Simulation (SAMOS VIII), Samos, Greece, July 2008.

[16]

Imran Rafiq Quadri and Samy Meftali and Jean-Luc Dekeyser. High Level Modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE. In Reconfigurable Communication-centric SoCs (ReCoSoC'08), Barcelona, Spain, July 2008.

[17]

Jehangir Khan, Smail Nair, Yassin Elhilali, and Jean-Luc Dekeyser. An MPSoC Architecture for the Multiple Target Tracking Application in Driver Assistant System. In 19th IEEE International Conference Application-specific Systems, Architectures and Processors (ASAP'08), Leuven, Belgium, July 2008.

[18]

Flori Glitia, Anne Etien, and Cedric Dumoulin. Traceability for an MDE Approach of Embedded System Conception. In Fourth ECMDA Tracibility Workshop, Berlin, Germany, June 2008.

[19]

Julien Taillard, Frédéric Guyomarc'h, and Jean-Luc Dekeyser. OpenMP code generation based on an Model Driven Engineering approach. In The 2008 High Performance Computing & Simulation Conference (HPCS 2008), Nicosia, Cyprus, June 2008.

[20]

Imran Rafiq Quadri, Samy Meftali, and Jean-Luc Dekeyser. A MDE design flow for implementing Partially Dynamically Reconfigurable FPGAs. In 2nd Colloque Nationale of GDR SOC-SIP, Paris, France, June 2008.

[21]

Cesar de Moura, Julien Taillard, Frédéric Guyomarc'h, and Cedric Dumoulin. Adaptation des Templates UML pour la modélisation de composants paramétrables : application à Gaspard2 . In 4èmes Jounées sur l'Ingénierie Dirigée par les Modèles (IDM 08), Mulhouse, France, June 2008.

[22]

Asma Charfi, Abdoulaye Gamatié, Antoine Honoré, Jean-Luc Dekeyser, and Mohamed Abid. Validation de modèles dans un cadre d'IDM dédié à la conception de systèmes sur puce. In 4èmes Jounées sur l'Ingénierie Dirigée par les Modèles (IDM 08), Mulhouse, France, June 2008.

[23]

Jean-Luc Dekeyser, Abdoulaye Gamatié, Anne Etien, Rabie Ben Atitallah, and Pierre Boulet. Using the UML Profile for MARTE to MPSoC Co-Design. In First International Conference on Embedded Systems & Critical Applications (ICESCA'08), Tunis, Tunisia, May 2008.

[24]

Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, and Jean-Luc Dekeyser. Using An MDE Approach for Modeling of Interconnection networks. In The International Symposium on Parallel Architectures, Algorithms and Networks Conference (ISPAN 08), Sydney, Australia, May 2008.

[25]

Abdoulaye Gamatié, Thierry Gautier, and Loïc Besnard. An interval-based solution for static analysis in the signal language. In 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), Belfast, Northern Ireland, pages 182–190. IEEE Computer Society, april 2008.

[26]

Éric Piel, Rabie Ben Atitallah, Philippe Marquet, Samy Meftali, Smaïl Niar, Anne Etien, Jean-Luc Dekeyser, and Pierre Boulet. Gaspard2: from marte to systemc simulation. In Proceeedings of the DATE'08 workshop on Modeling and Analyzis of Real-Time and Embedded Systems with the MARTE UML profile, March 2008.

[27]

Pierre Boulet. Formal semantics of Array-OL, a domain specific language for intensive multidimensional signal processing. Research Report RR-6467, INRIA, March 2008.

[28]

Rabie Ben Atitallah. Modèles et simulation des systèmes sur puce multiprocesseurs - Estimation des performances et de la consommation d'énergie. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, Lille, France, March 2008. (In French).

[29]

Hajer Chtioui, Rabie Ben Atitallah, Smail Niar, Mohamed Abid, and Jean-Luc Dekeyser. Gestion de la cohérence des caches dans les architectures MPSoC utilisant des NoC complexes. In Rencontres francophones du Parallélisme (RenPar'18) / Symposium en Architecture de machines (SympA '2008 ) / Conférence Française sur les Systèmes d'Exploitation (CFSE '6), Fribourg, Switzerland, February 2008.

[30]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, and Jean-Luc Dekeyser. Embedded Systems Specification and Design Languages, Selected papers from FDL 2007, chapter Model Transformations from a Data Parallel Formalism towards Synchronous Languages. Springer, 2008. (To appear).

[31]

Cedric Dumoulin and Anne Etien. Morphing de métamodèles. L'Objet, 13(4):33–35, October-December 2007.

[32]

Julien Taillard, Frédéric Guyomarc'h, and Jean-Luc Dekeyser. A graphical framework for high performance computing using an MDE approach. In 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Toulouse, France, February 2008.

[33]

Khaled Z. Ibrahim and Smail Niar. Power-aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC. TraKhalnsactions on High-Performance Embedded Architectures and Compilers, December 2007.

[34]

Yassine Aydi, Samy Meftali, Mohamed Abid, and Jean-Luc Dekeyser. Design and Performance Evaluation of a Reconfigurable Delta MIN for MPSOC. In 19th International Conference on Microelectronics (ICM'07), Cairo, Egypt, December 2007.

[35]

Éric Piel. Ordonnancement de systèmes parallèles temps-réel, De la modélisation à la mise en oe uvre par l'ingénierie dirigée par les modèles. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, Lille, France, December 2007. (In French).

[36]

Sébastien Le Beux. Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, Lille, France, December 2007. (In French).

[37]

Abou El Hassan Benyamina and Pierre Boulet. Multi-objective mapping for noc architecture. Journal of Digital Information Management, 5(6):378–384, December 2007.

[38]

Imran Rafiq Quadri, Samy Meftali, and Jean-Luc Dekeyser. An MDE Approach for Implementing Partial Dynamic Reconfiguration in FPGAs. In 16th International Conference on IP Based System-on-chip, IP'07, Grenoble, France, December 2007.

[39]

Rabie Ben Atitallah, Smail Niar, and Jean-Luc Dekeyser. MPSoC Power Estimation Framework at Transaction Level Modeling. In The 19th International Conference on Microelectronics (ICM 2007), Cairo, Egypt, December 2007.

[40]

Jean-Luc Dekeyser, Sébastien Le Beux, and Philippe Marquet. Une approche modèle pour la conception conjointe de systèmes embarqués hautes performances dédiés au transport. In Workshop International : Logistique & Transport (LT' 2007), Sousse, Tunisie, November 2007. (In French).

[41]

Yassine Aydi, Samy Meftali, Mohamed Abid, and Jean-Luc Dekeyser. Dynamicity Analysis of Delta MINs for MPSOC Architectures. In Conference internationale des sciences et = technique de l'automatique (ICM'07), Sousse, Tunisie, November 2007.

[42]

Souha Kamoun and Pierre Boulet. Une approche modèle pour la génération de scénarios de tests : Application au système ERTMS/ETCS. In Workshop International : Logistique and Transport 2007, Sousse, Tunisie, November 2007.

[43]

Souha Kamoun and Pierre Boulet. Model-Based Testing of the ERTMS System with SysML and MARTE. In MoDeVVa'07, Nashville, USA, October 2007.

[44]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, and Jean-Luc Dekeyser. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. Research Report RR-6291, INRIA, September 2007.

[45]

Rabie Ben Atitallah, Eric Piel, Smail Niar, Philippe Marquet, and Jean-Luc Dekeyser. Multilevel MPSoC simulation using an MDE approach. In IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, September 2007.

[46]

Rabie Ben Atitallah, Eric Piel, Julien Taillard, Smail Niar, and Jean-Luc Dekeyser. From High Level MPSoC description to SystemC Code Generation. In International ModEasy'07 Workshop in conjunction with Forum on specification and Design Languages (FDL'07), Barcelona, Spain, September 2007.

[47]

Pierre Boulet, Philippe Marquet, Éric Piel, and Julien Taillard. Repetitive Allocation Modeling with MARTE. In Forum on specification and design languages (FDL'07), Barcelona, Spain, September 2007. Invited paper, Author names alphabetically ordered.

[48]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, and Jean-Luc Dekeyser. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. In Forum on specification and design languages (FDL'07), Barcelona, Spain, September 2007.

[49]

Rabie Ben Atitallah, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Antoine Honoré, Ouassila Labbani, Sébastien Le Beux, Philippe Marquet, Éric Piel, Julien Taillard, and Huafeng Yu. Gaspard2 UML profile documentation. Technical Report 0342, INRIA, September 2007.

[50]

Sébastien Le Beux, Philippe Marquet, and Jean-Luc Dekeyser. A design flow to map parallel applications onto FPGAs. In 17th IEEE International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, August 2007.

[51]

Rabie Ben Atitallah, Smail Niar, Samy Meftali, and Jean-Luc Dekeyser. An MPSoC performance estimation framework using transaction level modeling. In The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Daegu, Korea, August 2007.

[52]

Sébastien Le Beux, Philippe Marquet, and Jean-Luc Dekeyser. Multiple Abstraction Views of FPGA to Map Parallel Applications. In Reconfigurable Communication-centric SoCs 2007 (ReCoSoC'07), Montpellier, France, June 2007.

[53]

Safouan Taha, Ansgar Radermacher, Sebastien Gerard, and Jean-Luc Dekeyser. An Open Framework for Detailed Hardware Modeling. In IEEE Second International Symposium on Industrial Embedded Systems, Lisbon, Portugal, June 2007.

[54]

Imran Rafiq Quadri, Pierre Boulet, and Jean-Luc Dekeyser. Modeling of topologies of interconnection networks based on multidimensional multiplicity. Research Report RR-6201, INRIA, May 2007.

[55]

Anne Etien, Cedric Dumoulin, and Emmanuel Renaux. Towards a unified notation to represent model transformation. Research Report RR-6187, INRIA, May 2007.

[56]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'06, chapter UML2 Profile for Modeling Controlled Data Parallel Applications. ChDL. Springer, 2007. (To appear).

[57]

Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, and Jean-Luc Dekeyser. Massively parallel processing on a chip. In ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.

[58]

Abou El Hassan Benyamina and Pierre Boulet. Multi-objective mapping for NoC architectures. In 1st International Conference on Digital Communications and Computer Applications, pages 132–139, Jordan, March 2007.

[59]

Pierre Boulet. Array-OL revisited, multidimensional intensive signal processing specification. Research Report RR-6113, INRIA, February 2007.

[60]

Abdoulaye Gamatié, Thierry Gautier, Paul Le Guernic, and Jean-Pierre Talpin. Polychronous design of embedded real-time applications. ACM Transactions on Software Engineering and Methodology, 2007. (To appear).

[61]

Abdoulaye Gamatié, Thierry Gautier, and Paul Le Guernic. Synchronous design of avionic applications based on model refinements. Journal of Embedded Computing, 2007. (To appear).

[62]

Ouassila Labbani, Éric Rutten, and Jean-Luc Dekeyser. Safe design methodology for an intelligent cruise control system with GPS. IEEE Intelligent Transportation Systems Society Newsletter, 8(4):16–23, December 2006.

[63]

Ashish Meena. Allocation, Assignation et Ordonnacement pour les Systèmes sur Puce Multi-Processeurs. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2006.

[64]

Simon Duquennoy, Sébastien Le Beux, Philippe Marquet, Samy Meftali, and Jean-Luc Dekeyser. MpNoC design: Modeling and simulation. In 15th IP Based SoC Design Conference (IP-SoC 2006), Grenoble, France, December 2006.

[65]

Lossan Bondé. Transformations de Modèles et Interopérabilité dans la Conception de Systèmes Hétérogènes sur Puce à Base d'IP. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2006. (In French).

[66]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous modeling of data-intensive applications. In International Open Workshop on Synchronous Programming (Synchron 2006), Alpe d'Huez, France, November 2006.

[67]

Ouassila Labbani. Modélisation à haut niveau du contrôle dans des applications de traitement systématique à parallélisme massif. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, November 2006. (In French).

[68]

Rabie Ben Atitallah, Lossan Bonde, Smail Niar, Samy Meftali, and Jean-Luc Dekeyser. Multilevel MPSoC performance evaluation using MDE approach. In International Symposium on System-on-Chip 2006 (SOC 2006), Tampere, Finland, November 2006. Invited paper.

[69]

Jean-Pierre Talpin, Christan Brunette, Thierry Gautier, and Abdoulaye Gamatié. Polychronous mode automata. In 6th Annual ACM Conference on Embedded Software (EMSOFT'06), Seoul, South Korea, October 2006.

[70]

Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet, and Jean-Luc Dekeyser. Vers des transformations d'applications à parallélisme de données en équations synchrones. In 9e édition de SYMPosium en Architectures nouvelles de machines (SympA'2006), Perpignan, France, October 2006.

[71]

Ouassila Labbani, Éric Rutten, and Jean-Luc Dekeyser. Safe design methodology for an intelligent cruise control system with GPS. In 64th IEEE Vehicular Technology Conference (VTC 2006), Montréal, Québec, Canada, September 2006.

[72]

Laila Sakkila, Pascal Deloof, Yassin El Hillali, Atika Rivenq, and Smail Niar. A real time signal processing for an anticollision road radar system. In 64th IEEE Vehicular Technology Conference (VTC 2006), Montréal, Québec, Canada, September 2006.

[73]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. UML2 profile for modeling controlled data parallel applications. In Forum on specification and Design Languages (FDL'06), Darmstadt, Germany, September 2006.

[74]

Alain Girault and Huafeng Yu. A flexible method to tolerate value sensor failures. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2006), pages 86–93, Prague, Czech Republic, September 2006.

[75]

Pierre Boulet, Cédric Dumoulin, and Antoine Honoré. From MDD concepts to experiments and illustrations, chapter Model Driven Engineering for System-on-Chip Design. ISTE, Hermes science and Lavoisier, September 2006.

[76]

Sébastien Le Beux, Vincent Gagné, El Mostapha Aboulhamid, Philippe Marquet, and Jean-Luc Dekeyser. Hardware/software exploration for an anti-collision radar system. In 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico, August 2006.

[77]

Jamel Tayeb and Smail Niar. Adapting the EPIC register stack for an efficient execution of Forth. In 22nd EuroForth Conference (EuroForth 2006), Cambridge, England, September 2006.

[78]

Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, and Jean-Luc Dekeyser. FPGA implementation of embedded cruise control and anti-collision radar. In 9th Euromicro Conference on Digital System Design (DSD'2006), Dubrovnik, Croatia, August 2006.

[79]

Jamel Tayeb and Smail Niar. Adapting EPIC architecture's register stack for virtual stack machines. In 9th Euromicro Conference on Digital System Design (DSD'2006), Dubrovnik, Croatia, August 2006.

[80]

Abdoulaye Gamatié, Christian Brunette, Romain Delamare, Thierry Gautier, and Jean-Pierre Talpin. A modeling paradigm for integrated modular avionic design. In Euromicro Conference Software Engineering and Advanced Application (SEAA'06), Cavtat/Dubrovnik, Croatia, August 2006.

[81]

Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Mohan Tahar Kechadi, and Isaac D. Scherson. A universal performance factor for multi-criteria evaluation of multistage interconnection networks. Future Generation Computer Systems, 22(7):794–804, 2006.

[82]

Imran Quadri. Modélisation de topologies de réseaux d'interconnexion à base de multiplicités multidimensionnelles. Mémoire de DEA, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, June 2006.

[83]

Laurence Duchien and Cédric Dumoulin, editors. IDM06, Actes des 2e Journées sur l'Ingénierie Dirigée par les Modèles. Hermès, Lille, France, June 2006. ISBN 2-7261-1290-8.

[84]

Smail Niar and Nicolas Inglart. Rapid performance and power consumption estimation methods for embedded system design. In IEEE International Workshop on Rapid System Prototyping (RSP'2006), Chania, Crete, June 2006.

[85]

Cédric Dumoulin, Arnaud Cuccuru, and Antoine Honoré. Motifs pour la métamodélisation : Relation, relation dirigée, association. In 2e journées sur l'Ingénierie Dirigée par les Modèles (IDM'06), pages 217–222, Lille, France, June 2006. (In French).

[86]

Loïc Besnard, Hervé Marchand, and Éric Rutten. The Sigali tool box. In 8th Workshop on Discrete Event Systems (WODES'06), Tools session, Ann Arbor, MI, July 2006.

[87]

Gwenaël Delaval and Eric Rutten. A domain-specific language for multi-task systems, applying discrete controller synthesis. In 21st ACM Symposium on Applied Computing (SAC 2006), Special Track on Embedded Systems: Applications, Solutions, and Techniques, pages 901–905, Dijon, France, April 2006.

[88]

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet, and Jean-Luc Dekeyser. Synchronous modeling of data intensive applications. Research Report 5876, INRIA, April 2006.

[89]

Eric Piel, Philippe Marquet, Julien Soula, and Jean-Luc Dekeyser. Real-time systems for multi-processor architectures. In 14th International Workshop on Parallel and Distributed Real-Time Systems, In conjunction with IPDPS, 20th IEEE International Parallel and Distributed Processing Symposium, Island of Rhodes, Greece, April 2006. IEEE Computer Society Press. Invited paper.

[90]

Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Algorithms and Tools for Parallel Computing On Heterogeneous Clusters, chapter Towards Distributed Process Networks with CORBA. Nova Science Publishers, Inc, 2006. ISBN: 1-60021-049-X.

[91]

Hassan Sbeyti, Smail Niar, and Lieven Eeckhout. Pattern-driven prefetching for multimedia applications on embedded processors. Journal of Systems Architecture, 52(4):199–212, April 2006.

[92]

Rabie Ben Atitallah, Smail Niar, Alain Greiner, Samy Meftali, and Jean Luc Dekeyser. Estimating energy consumption for an MPSoC architectural exploration. In Architecture of Computing Systems (ARCS'06), Frankfurt, Germany, March 2006.

[93]

Abdoulaye Gamatié, Thierry Gautier, and Paul Le Guernic. Towards static analysis of SIGNAL programs using interval techniques. In Synchronous Languages, Applications, and Programming (SLAP'06), Vienna, Austria, March 2006.

[94]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Separating control and data flow: Methodology and automotive system case study. Research Report RR-5832, INRIA, France, January 2006.

[95]

Julien Taillard, Jean-Luc Dekeyser, and Francis Piriou. A design of a UML profile for meta-computing. In 14th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2006), Montbéliard-Sochaux, France, February 2006.

[96]

Sébastien Le Beux, Vincent Gagné, El Mostapha Aboulhamid, Philippe Marquet, and Jean-Luc Dekeyser. Hardware/software exploration for an anti-collision radar system. Research Report 5820, INRIA, January 2006.

[97]

Sébastien Le Beux, Philippe Marquet, and Jean-Luc Dekeyser. FPGA configuration of intensive multimedia processing tasks modeled in UML. Research Report RR-5810, INRIA, France, January 2006.

[98]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Introducing control in the Gaspard2 data-parallel metamodel: Synchronous approach. Research Report RR-5794, INRIA, France, January 2006.

[99]

Luc Charest, Philippe Marquet, Jean-Luc Dekeyser, El Mostapha Aboulhamid, and Guy Bois. Using design pattern for type unification, structural unification, semantic clarification and introspection in SystemC. Annals for Micro and Nano Systems, 2005. (Accepted for publication).

[100]

Samy Meftali, Joël Vennin, and Jean-Luc Dekeyser. An optimized distributed simulation environment for SoC design. Annals for Micro and Nano Systems, 2005. (Accepted for publication).

[101]

Ali Koudri, Samy Meftali, and Jean-Luc Dekeyser. IP integration in embedded systems modeling. In 14th IP Based SoC Design Conference (IP-SoC 2005), Grenoble, France, December 2005.

[102]

Samy Meftali, Jean-Luc Dekeyser, and Isaac D. Scherson. Scalable multistage networks for multiprocessor System-on-Chip design. In 8th International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005.

[103]

Philippe Dumont. Spécification multidimensionnelle pour le traitement du signal systématique. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2005. (In French).

[104]

Mickaël Samyn. Une simulation fonctionnelle d'un système monopuce dédié au traitement du signal intensif - Une approche dirigée par les modèles. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2005. (In French).

[105]

Éric Piel, Philippe Marquet, Julien Soula, Christophe Osuna, and Jean-Luc Dekeyser. ARTiS, an asymmetric real-time scheduler for Linux on multi-processor architectures. Research Report RR-5781, INRIA, France, December 2005.

[106]

Abdelkader Amar, Pierre Boulet, and Philippe Dumont. Projection of the Array-OL specification language onto the Kahn process network computation model. In International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005.

[107]

Julien Taillard, Philippe Marquet, and Jean-Luc Dekeyser. Embedded Linux co-simulation. In eIP Based SoC Design Conference (IP-SoC 2005), Grenoble, France, December 2005.

[108]

Arnaud Cuccuru. Modélisation unifiée des aspects répétitifs dans la conception conjointe logicielle/matérielle des systèmes sur puce à hautes performances. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, November 2005. (In French).

[109]

Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, and Pierre Boulet. Towards UML 2 extensions for compact modeling of regular complex topologies - A partial answer to the MARTE RFP. In MoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, pages 445–459, Montego Bay, Jamaica, October 2005. Lecture Notes in Computer Science vol. 3713.

[110]

Smail Niar. Contribution à la conception de nouvelles micro-architectures : de retour vers les multiprocesseurs via l'embarqué. Habilitation à diriger des recherches, Université de Valenciennes et du Hainaut-Cambrésis, Valenciennes, France, October 2005. (In French).

[111]

Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, and Éric Rutten. Introducing control in the Gaspard2 data-parallel metamodel: Synchronous approach. In International Workshop MARTES: Modeling and Analysis of Real-Time and Embedded Systems (in conjunction with 8th International Conference on Model Driven Engineering Languages and Systems), MoDELS/UML 2005, Montego Bay, Jamaica, October 2005.

[112]

Ashish Meena and Pierre Boulet. Model driven scheduling framework for multiprocessor SoC design. In Workshop on Scheduling for Parallel Computing (SPC 2005), Poznan, Poland, September 2005. ©Springer-Verlag.

[113]

Eric Piel, Philippe Marquet, Julien Soula, and Jean-Luc Dekeyser. Asymmetric scheduling and load balancing for real-time on Linux SMP. In Workshop on Scheduling for Parallel Computing (SPC 2005), Poznan, Poland, September 2005. Lecture Notes in Computer Science vol. 3911. ©Springer-Verlag.

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Joël Vennin, Stéphane Penain, Luc Charest, Samy Meftali, and Jean-Luc Dekeyser. Embedded scripting inside SystemC. In Forum on Specification and Design Languages (FDL'05), Lausanne, Switzerland, September 2005.

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Samy Meftali Samy, Anouar Dziri, Luc Charest, Philippe Marquet, and Jean-Luc Dekeyser. SOAP based distributed simulation environment for System-on-Chip (SoC) design. In Forum on Specification and Design Languages, FDL'05, Lausanne, Switzerland, September 2005.

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H. Alla and E. Rutten, editors. Modélisation des Systèmes Réactifs, Autrans (Grenoble), France, October 2005. Journal Européen des Systèmes Automatisés, vol. 39, Hermès.

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Lieven Eeckhout, Smaïl Niar, and Koen De Bosschere. Optimal sample length for efficient cache simulation. Journal of Systems Architecture, 51(9):513–525, September 2005.

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Pierre Boulet, editor. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'04. ChDL. Springer, 2005.

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Lossan Bondé, Pierre Boulet, and Jean-Luc Dekeyser. Traceability and interoperability at different levels of abstraction in model transformations. In Forum on Specification and Design Languages, FDL'05, Lausanne, Switzerland, September 2005.

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Lossan Bondé, Cédric Dumoulin, and Jean-Luc Dekeyser. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'04, chapter Metamodels and MDA Transformations for Embedded Systems. ChDL. Springer, 2005.

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Arnaud Cuccuru, Robert De Simone, Thierry Saunier, Günther Siegel, and Yves Sorel. P2I: An innovative MDA methodology for embedded real-time system. In 8th Euromicro Conference on Digital System Design (DSD'2005), pages 29–33, Porto, Portugal, August 2005.

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Lossan Bondé, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet, Samy Meftaly, and Mickaël Samyn. Model Driven Engineering for Distributed Embedded Real-Time Systems, chapter Model Driven Architecture for Intensive Embedded Systems. ISTE, Hermes science and Lavoisier, August 2005. edited by Sébastien Gérard, Jean-Philippe Babeau and Joël Champeau.

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Gwenaël Delaval and Éric Rutten. A domain-specific language for multi-task systems, applying discrete controller synthesis. Research Report RR-5690, INRIA, September 2005.

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Julien Taillard. Modélisation d'IP pour la simulation SystemC d'OS de type Linux embarqué. Mémoire de DEA, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, July 2005. (In French).

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Jean-Luc Dekeyser, Pierre Boulet, Philippe Marquet, and Samy Meftali. Model driven engineering for soc co-design. In NEWCAS'05, Québec, Québec, June 2005. IEEE.

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Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, and Ashish Meena. Model driven engineering for regular MPSoC co-design. In ReCoSoC-05, Montpellier, France, June 2005.

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Luc Charest and Philippe Marquet. Comparisons of different approaches of realizing IP block configuration in SystemC. In The 3rd International IEEE Northeast Workshop on Circuits & Systems, Québec City, Canada, June 2005.

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L. Rioux, T. Saunier, S. Gerard, A. Radermacher, R. de Simone, T. Gautier, Y. Sorel, J. Forget, J.-L. Dekeyser, A. Cuccuru, C. Dumoulin, and C. Andre. MARTE: A new OMG profile RFP for the modeling and analysis of real-time embedded systems. In DAC 2005 Workshop UML for SoC Design (UML-SoC'05), Anaheim, CA, USA, June 2005.

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Jean-Luc Dekeyser, Philippe Marquet, Samy Meftali, Cédric Dumoulin, Pierre Boulet, and Smail Niar. Why to do without Model Driven Architecture in embedded system codesign?. In The first annual IEEE BENELUX/DSP Valley Signal Processing Symposium, (SPS-DARTS 2005), Antwerp, Belgium, April 2005.

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Philippe Marquet, Éric Piel, Julien Soula, and Jean-Luc Dekeyser. ARTiS, un système d'exploitation temps-réel asymétrique. In 4e édition de la Conférence Française sur les Systèmes d'Exploitation (CFSE'4), Le Croisic, France, April 2005. (In French).

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Ouassila Labbani, Jean-Luc Dekeyser, and Pierre Boulet. Mode-automata based methodology for scade. In Springer, editor, Hybrid Systems: Computation and Control, 8th International Workshop, LNCS series, pages 386–401, Zurich, Switzerland, March 2005.

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Abdelkader Amar, Pierre Boulet, and Philippe Dumont. Projection of the Array-OL specification language onto the Kahn process network computation model. Research Report RR-5515, INRIA, March 2005.

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Philippe Dumont and Pierre Boulet. Another multidimensional synchronous dataflow: Simulating Array-OL in Ptolemy II. Research Report RR-5516, INRIA, March 2005.

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Arnaud Cuccuru, Philippe Marquet, and Jean-Luc Dekeyser. IFIP International Federation for Information Processing, volume 176, chapter UML2 as an ADL Hierarchichal Hardware Modeling, pages 133–147. Springer, January 2005.

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Smail Niar and Jamel Tayeb. Programmation et optimisation d'applications pour les processeurs Intel Itanium. Eyrolles, January 2005.

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Pierre Boulet and Ashish Meena. The case for globally irregular locally regular algorithm architecture adequation. In Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA'05), Dijon, France, January 2005.

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Joël Vennin, Samy Meftali, and Jean-Luc Dekeyser. Understanding and extending SystemC user thread package to IA-64 platform. In International Workshop on IP Based SoC design (IP-SoC 2004), Grenoble, France, December 2004.

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Smail Niar, Samy Meftali, and Jean-Luc Dekeyser. Power aware cache memory design with SystemC. In 16th International Conference on Microelectronics (ICM 2004), pages 244– 247, Tunis, Tunisia, December 2004.

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Philippe Marquet, Éric Piel, Julien Soula, and Jean-Luc Dekeyser. Implementation of ARTiS, an asymmetric real-time extension of SMP Linux. In Sixth Realtime Linux Workshop, Singapore, November 2004.

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ITEA Hyades Project. Linux for high performance and real-time computing on SMP systems. In Sixth Realtime Linux Workshop, Singapore, November 2004.

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Emilian Turbatu, Samy Meftali, Smaïl Niar, and Jean-Luc Dekeyser. An automatic communication synthesis for high level SoC design using transaction level modeling. In FDL04, Lille, France, September 2004.

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Mickaël Samyn, Samy Meftali, and Jean-Luc Dekeyser. MDA based, SystemC code generation, applied to intensive signal processing applications. In FDL04, Lille, France, September 2004.

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Lossan Bondé, Cédric Dumoulin, and Jean-Luc Dekeyser. Metamodels and MDA transformations for embedded systems. In FDL04, Lille, France, September 2004.

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Arnaud Cuccuru, Pierre Boulet, and Jean-Luc Dekeyser. Regular hardware architecture modeling with UML2. In FDL04, Lille, France, September 2004.

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Samy Meftali and Jean-Luc Dekeyser. SoC P2P: A peer-to-peer IP based SoCs design and simulation tool. In 5th IFIP Working Conference on Virtual Enterprises (PRO-VE'04), Toulouse, France, August 2004.

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Samy Meftali and Jean-Luc Dekeyser. An optimal charge balancing model for fast distributed SystemC simulation in IP/SoC design. In The 4th IEEE International Workshop System-on-Chip for Real-Time Applications (IWSOC 04), Banff, Alberta, Canada, July 2004.

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Ahmad Chadi Aljundi. Une Méthodologie Multi-Critères Pour l'Évaluation de Performance Appliquée aux Architectures de Réseaux d'Interconnexion Multi-Étages. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, July 2004. (In French).

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Éric Piel, Philippe Marquet, Julien Soula, and Jean-Luc Dekeyser. Load-balancing for a real-time system based on asymmetric multi-processing. In 16th Euromicro Conference on Real-Time Systems, WIP session, Catania, Italy, June 2004. See [PMSD04rr06].

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Éric Piel. Équilibrage de charge pour systèmes temps-réel asymétriques sur multi-processeurs. Mémoire de DEA, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, June 2004. (In French).

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Javed Dulloo and Philippe Marquet. Design of a real-time scheduler for Kahn Process Networks on multiprocessor systems. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'04), Las Vegas, NV, USA, June 2004. See [DuMa03rr06].

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Éric Piel, Philippe Marquet, Julien Soula, and Jean-Luc Dekeyser. Load-balancing for a real-time system based on asymmetric multi-processing. Research Report 2004-06, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, April 2004.

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Philippe Marquet, Julien Soula, Éric Piel, and Jean-Luc Dekeyser. An asymmetric model for real-time and load balancing on Linux SMP. Research Report 2004-04, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, April 2004.

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Arnaud Cuccuru, Philippe Marquet, and Jean-Luc Dekeyser. UML2 as an ADL hierarchichal hardware modeling. Research Report RR-5166, INRIA, April 2004.

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Ahmad Chadi Aljundi and Jean-Luc Dekeyser. The effect of the degree of multistage interconnection networks on their performance: the case of delta and over-sized delta networks. In 12th Euromicro Conference on Parallel, Distributed and Network-Based Processing (EUROMICRO-PDP'04), A Coruña, Spain, February 2004.

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Samy Meftali, Joël Vennin, and Jean-Luc Dekeyser. Automatic generation of geographically distributed system simulation models for IP/SoC design. In The 46th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 03), Cairo, Egypt, December 2003.

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Abdelkader Amar. Support d'exécution pour le metacomputing à l'aide de CORBA. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2003. (In French).

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Samy Meftali, Joël Vennin, and Jean-Luc Dekeyser. A fast SystemC simulation methodology fo multi-level IP/SoC design. In IFIP International Workshop on IP Based System-on-Chip Design, Grenoble, France, November 2003.

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Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet, Philippe Kajfasz, and Dominique Ragot. Sophocles: Cyber-enterprise for System-on-Chip distributed simulation – Model unification. In IFIP International Workshop on IP Based System-on-Chip Design, Grenoble, France, November 2003.

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Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, and Philippe Marquet. MDA for SoC embedded design, intensive signal processing experiment. In SIVOES-MDA, San Francisco, USA, November 2003. Extended version of [DBDM03fdl].

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Javed Dulloo and Philippe Marquet. Design of a real-time scheduler for Kahn Process Networks on multiprocessor systems. Research Report 03-06, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, November 2003.

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Cédric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, and Philippe Marquet. MDA for SoC design, intensive signal processing experiment. In FDL'03, Frankfurt, Germany, September 2003. ECSI.

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Momtchil Momtchev. Éléments d'implantation d'un noyau ARTiS. Research Report 03-05, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, September 2003. (In French).

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Cédric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, Stéphane Pulon, and Gérard Cristau. Interoperability between design and simulation tools using model transformation techniques. In FDL'03, Frankfurt, Germany, September 2003. ECSI.

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Ahmad Chadi Aljundi, Jean-Luc Dekeyser, and Isaac D. Scherson. An interconnection networks comparative performance evaluation methodology: The case of delta and over-sized delta multistage interconnection networks. In Proceedings of the 16th International Conference on Parallel and Distributed Computing Systems, Reno, Nevada, USA, August 2003.

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Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Tahar Kechadi, and Isaac D. Scherson. A study of an evaluation methodology for unbuffered multistage interconnection networks. In International Parallel and Distributed Processing Symposium (IPDPS'03), Nice, France, April 2003.

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Cédric Dumoulin, Pierre Boulet, Jean-Luc Dekeyser, and Philippe Marquet. UML 2.0 structure diagram for intensive signal processing application specification. Research Report RR-4766, INRIA, March 2003.

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Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, and Frans Theeuwen. Distributed process networks using half FIFO queues in CORBA. Research Report RR-4765, INRIA, March 2003.

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Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Towards distributed process networks with CORBA. Scalable Computing: Practice and Experience, 5(4), December 2002.

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Philippe Dumont. Étude des transformations d'un code Array-OL dans Gaspard. Research Report 02-11, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, September 2002.

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Cédric Dumoulin and Jean-Luc Dekeyser. UML framework for intensive signal processing embedded applications. Research Report 02-07, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, July 2002.

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Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Kajfasz, Philippe Marquet, and Dominique Ragot. Sophocles: Cyber-enterprise for system-on-chip distributed simulation – model unification. Research Report 02-06, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, June 2002.

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Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Towards distributed process networks with CORBA. Research Report 02-04, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, May 2002.

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Momtchil Momtchev and Philippe Marquet. CacheFS : un système de fichiers distribué all-cache. In Rencontres Francophones de l'ASF, section française de l'ACM-SIGOPS, (ASF'02), Hammamet, Tunisie, April 2002. (In French).

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Momtchil Momtchev and Philippe Marquet. An asymmetric real-time scheduling for Linux. In Tenth International Workshop on Parallel and Distributed Real-Time Systems, Fort Lauderdale, FL, USA, April 2002.

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Julien Soula. Principe de Compilation d'un Langage de Traitement de Signal. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, December 2001. (In French). (Gzipped PostScript, 152 pages, 1203687 bytes)

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Momtchil Momtchev and Philippe Marquet. CacheFS : Un système de fichiers distribué all-cache. Research Report 01-12, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, December 2001.

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Momtchil Momtchev and Philippe Marquet. An open operating system for intensive signal processing. Research Report 01-08, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, October 2001.

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Abdelkader Amar, Pierre Boulet, and Jean-Luc Dekeyser. Assembling dynamic components for metacomputing using CORBA. In Parallel Computing 2001, Naples, Italy, September 2001. Lecture Notes in Computer Science.

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Julien Soula, Philippe Marquet, Jean-Luc Dekeyser, and Alain Demeure. Compilation principle of a specification language dedicated to signal processing. In Sixth International Conference on Parallel Computing Technologies, PaCT 2001, pages 358–370, Novosibirsk, Russia, September 2001. Lecture Notes in Computer Science vol. 2127.

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Pierre Boulet, Jean-Luc Dekeyser, Florent Devin, and Philippe Marquet. A visual development environment for meta-computing applications. In HCI International 2001, 9th Int'l Conf. on Human-Computer Interaction, New Orleans, LA, USA, August 2001. Lawrence Erlbaum Associates, Publishers.

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, and François Piriou. Parallelization of a 3-D magnetostatic code using high performance fortran and the schur complement method. In Conference on the Computation of Electromagnetic Fields, Compumag'13, Évian, France, July 2001.

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, and François Piriou. Une approche génie logiciel des codes de simulation irréguliers : Application au cas de l'electromagnétisme. In RenPar'13, Rencontres Francophones du Parallélisme des Architectures et des Systèmes, pages 115–120, Paris, France, June 2001. (In French).

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Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, and Alain Demeure. Visual data-parallel programming for signal processing applications. In 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, pages 105–112, Mantova, Italy, February 2001.

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Emmanuel Cagniot. Algorithmes Data-parallèles Irréguliers Appliqués à la Simulation Éléctromagnétique Tridimensionelle. Thèse de doctorat (PhD Thesis), Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, December 2000. (In French).

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, and Stéphane Clenet. High level parallelization of a 3D electromagnetic simulation code with irregular communication patterns. In 4th International Meeting on Vector and Parallel Processing (VECPAR'2000), pages 519–528, Porto, Portugal, June 2000. Lecture Notes in Computer Science vol. 1470.

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, and François Piriou. Parallélisation d'un code electromagnétique 3D irrégulier avec High Performance Fortran. In RenPar'12, Rencontres Francophones du Parallélisme des Architectures et des Systèmes, pages 237–243, Besançon, France, June 2000. (In French).

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Fabien Banse, Jean-Luc Dekeyser, and Renaud Fauquembergue. Parallélisation d'une méthode de Montè-Carlo pour la simulation de composants semi-conducteurs. Technique et Science Informatiques, 19(8), 2000. (In French).

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, and Georges Marques. Parallelization of 3D magnetostatic code using High Performance Fortran. In International Conference on Parallel Computing in Electrical Engineering, PARELEC'2000, pages 181–185, Trois-Rivières, Quebec, Canada, August 2000.

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Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, François Piriou, and Georges Marques. Parallélisation d'un code 3D magnétostatique avec le langage de programmation High Performance Fortran. In Conférence Européenne sur les Méthodes Numériques en Éléctomagnétisme, NUMELEC'2000 (poster session), pages 184–185, Poitiers, France, March 2000. (In French).

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Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, and Alain Demeure. Visual data-parallel programming for signal processing applications. Research Report 00-05, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, February 2000.

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Pierre Boulet and Xavier Redon. SPPoC : fonctionnement et applications. Research Report 00-04, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, February 2000.

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Julien Soula, Philippe Marquet, Jean-Luc Dekeyser, and Alain Demeure. Compilation principle of a specification language dedicated to signal processing. Research Report 00-03, Laboratoire d'Informatique Fondamentale de Lille, Université de Lille 1, France, January 2000.

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Pierre Boulet and Xavier Redon. SPPoC: Symbolic parameterized polyhedral calculator. In Workshop Compilation et Parallélisation Automatique, St Nabor, France, October 1999. (In French). Slides of the presentation.

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Jean-Luc Dekeyser, Philippe Marquet, and Julien Soula. Video kills the radio stars. In Supercomputing'99 (poster session), Portland, OR, USA, November 1999.

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Pierre Boulet, Jean-Luc Dekeyser, Alain Demeure, Florent Devin, and Philippe Marquet. Une approche à la SQL du traitement de données intensif dans Gaspard. In RenPar'11, Rencontres Francophones du Parallélisme des Architectures et des Systèmes, Rennes, France, June 1999. (In French).

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Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, François Piriou, Pierre Boulet, Stéphane Clénet, Yvonnick Le Menach, and Georges Marques. Parallelization of a Fortran 90 program for electromagnetic problems. In 3rd Annual HPF User Group Meeting, HUG'99, Redondo Beach, CA, USA, August 1999.

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Pierre Boulet and Xavier Redon. Communication pre-evaluation in HPF. In Euro-Par'98, pages 263–272. Lecture Notes in Computer Science vol. 1470, 1998.

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Feb 9 2007, 17:38.