Research Activities

 

Areas of interests

  • Dynamic reconfigurable architectures and systems
  • MultiProcessor System-on-Chip (MPSoC) design
  • Performance and enegy consumption modeling, estimation, and optimization
  • Design space exploration
  • Simulation speedup using Transaction Level Modeling (TLM)

PhD and Master's degree students

Former PhD and Master students

Current projects

  • The ANR project OpenPeople: Open-Power and Energy Optimization PLatform and Estimator
    • Partners: UBS-LAB-STICC, UVHC-INRIA Lille Nord Europe, LEAT-UNSA, INRIA Nancy Grand Est, UR1-IRISA-Cairn, THALES Communications, InPixal.

    OPEN-PEOPLE stands for Open Power and Energy Optimization PLatform and Estimator. The platform is defined for estimation and optimization of the power and energy consumption of complex electronic systems. Among the target systems, we mention heterogeneous MPSoC such as the TI OMAP 3530 and reconfigurable circuits like the Xilinx Virtex5 FPGA. Our platform allows power estimation using:

    • direct access to the hardware execution boards and the measurement equipments. This first alternative enables designer to measure the real power dissipation of the target system. To do so, the low level description of the system (C, VHDL, etc.) is carried out natively on the target board. Furthermore, this alternative is used to build new power models for hardware or software components.

    • a set of Electronic System Level (ESL) tools coupled with accurate power models elaborated within the first alternative. Mainly, we offer tools at the functional and transactional levels in the context of multilevel exploration of new complex architectures.

    The figure below presents a global view of the platform which is based on two main parts; the software part and the hardware part. The software user interface ensures the access to the power measurements and helps the designer to define energy models for the hardware and software system components. From the measurements, the designer can build models and compute an estimation of the energy and/or power consumption of its system. In addition, from this software user interface, the hardware platform can be controled. The hardware part consists of the embedded system boards, the measurement equipments, and the computer that controls these different elements and schedules the list of measurements required by different users. Various research and development works are currently done in the OPEN-PEOPLE project. These works include the definition of new methods and tools to model the different components of an heterogeneous system architecture: processors, hardware accelerators, memories, reconfigurable circuits, operating system services, IP blocks, etc. For reconfigurable system, the dynamic reconfiguration paradigm will be modeled to estimate how this feature can be used by Operating System (OS) to reduce the energy consumption. Furthermore, this project studies how the complete estimation and validation can be performed for very complex systems with a small simulation time.

    Short OpenPeople presentation can be found here.

  • The CHART project: Co-design modeling and High-performance ARchitecture for Test and Simulation
    • Partners: EADS IW, Eurocopter, UVHC, Lille1.

    Test Systems have always been considered as an essential part in the avionic development cycle. Due to the everchanging face of technology, the Eurocopter research department leads to the development of Pro-Active Test Systems. The objective of this project is to bring reliability and competitiveness to the avionic industry. In the first quarter of 2010, the development of new test system has been started.

    In present industrial practice, different test benches are used for the verification of various helicopter ranges (EC175, EC135, etc.) and Unit(s)-Under-Test (UUTs) (automatic pilot, navigation, etc.). Each test bench relies on a specific hardware architecture and software tools. This is due to the heterogeneity of the helicopter parts (which are under test) in terms of computing requirements and handled data structures. In general, several specialised CPU boards are needed to satisfy real time constraints which leads to sophisticated synchronization and communication schemes. In addition to this, dedicated avionic I/O boards (Arinc 429, 1553, etc.) are required depending on the UUTs. This test methodology calls for separate teams with different domain experts in order to achieve the test of each part. The overall avionic system verification is done through the first prototype of the helicopter. Today, this test process is very complex and expensive to perform.

    This project addresses the above test methodology limitations and calls for an innovative avionic test environment. Our main objective is to build up a generic test environment by the means of offering more flexibility regarding the selection of the suitable target avionic system. An efficient test methodology favors the reuse and the interoperability of hardware and software models while switching between different scenarios. Furthermore, automation in manufacturing process is a key for increasing the productivity and reducing the cost.

    Our contributions in the avionic test environment domain can be summarized as follows:

    • First, we proposed a hybrid CPU/FPGA architecture for the test system. Indeed, today multicore CPUs come with high computation rates while the FPGA offers flexibility and adaptability to the system. Within our environment, a great care has been devoted to the real time aspect in order to satisfy tight computing and communication deadlines. Our proposal relies on industrial and certified technologies that can be embedded easily on the final avionic product.

    • Second, we defined an efficient methodology that makes profit from the hybrid architecture to adapt the test system according to the target realization. The reuse and the interoperability advantages are ensured in this methodology with the help of the reconfigurable technology.

    More details are included in this aerospace testing international magazine article.

Previously

According to Moore’s law, more and more transistors will be integrated on a single chip. Such a huge transistor budget makes it increasingly difficult for engineers to design and verify the very complex chips that result, and in turn widens the gap between silicon capacity and design productivity. MultiProcessor Systems-on-Chip (MPSoC) architecture has thus become a solution for designing embedded systems dedicated to applications that require intensive computations. The most important design challenges in such systems consists in solving the huge architectural solution space appropriately. In fact, MPSoC are generally very heterogeneous, that can, for example, contain memories (Cache, SRAM, FIFO...), processors (MCU, DSP...), interconnecting elements (Bus, Crossbar, NoC...), I/O peripherals and FPGA.

An efficient and fast design space exploration (DSE) of such systems needs a set of tools capable of estimating performance and energy at higher abstraction level in the design flow. Nowadays, energy consumption has emerged as a primary design metric when developing MPSoC circuit taking into account silicon integration, IP multiplicity and clock frequency rise. Traditional approaches for performance and energy estimation at the Register Transfer Level (RTL) cannot adequately support the level of complexity needed for future MPSoC, since RTL tools require great quantities of simulation time to explore the huge architectural solution space. Recently, significant research efforts have been expended to evaluate MPSoC architectures at the CABA (Cycle Accurate Bit Accurate) level in an attempt to reduce simulation time. Usually, to move from the RTL to the CABA level, hardware implementation details are hidden from the processing part of the system, while preserving system behavior at the clock cycle level. Though using the CABA level has allowed accurate performance estimation, MPSoC DSE at this level is not yet sufficiently rapid compared to RTL.

In our work, we focus on the use of Transaction Level Modeling (TLM) in an MPSoC design which corresponds to a set of abstraction levels that simplifies the description of inter-module communication transactions using objects and channels between the communicating modules. Consequently, modeling MPSoC architectures becomes easier and faster than at the CABA level. As our objective is to propose reliable environmentfor rapid MPSoC DSE, the framework has been designed in the context of timed Programmer’s View (PVT) level. In the conventional definition of the PVT level, the hardware architecture is specified for both processing and communication parts, as well as some arbitration of the communication infrastructure is applied. In addition for performance estimation, this level is annotated with timing specification [1].

To reduce the complexity of MPSoC design, we focus on the use of Model-Driven Engineering (MDE). This methodology is centered around two concepts: model and transformation. Data and their structures are represented in models, while the computation is done by transformations. Models contain information structured according to the metamodel they conform to. In our framework, models are used to represent the MPSoC (application, architecture, and allocation). Transformations are employed to move from an abstract model to a detailed model. The set of transformations forms the compilation chain. In our case, this chain converts the platform-independent MPSoC model into a platform dependent. In our case you obtained a SystemC simulation code at the CABA or PVT level [2] (figure 1). At each level, tools for performance and energy estimation are developed[3][4][5]. This framework is integrated in our environment Gaspard 2 [6]. The MDE methodology provides great flexibility on the compilation chain. Thus, designers can couple additional tools, or target different platforms. For instance we have also carried out the generation of VHDL implementation on FPGA and of synchronous language code from the same chain.

Our Gaspard 2 Environment can be downloaded from here.

My PhD thesis

Multiprocessor system on chip (MPSoC) simulation in the first design steps has an important impact in reducing the time to market of the final product. However, MPSoC have become more and more complex and heterogeneous. Consequently, traditional approaches for system simulation at lower levels cannot adequately support the complexity needed for the design of future MPSoC. In this thesis, we propose a framework composed of several simulation levels. This enables early performance evaluation in the design flow. The proposed framework is useful for design space exploration and permits to find rapidly the most adequate Architec- ture/Application configuration. In the first part of this thesis, we present an efficient simulation tool composed of three levels that offer several performance/energy tradeoffs. The three levels are differentiated by the accuracy of architectural descriptions based on the SystemC-TLM standard. In the second part, we are interested by the MPSoC energy consumption. For this, we enhanced our simulation framework with flexible and accurate energy consumption models. Finally in the third part, a compilation chain based on a Model Driven Engineering (MDE) approach is developed and integrated in the Gaspard environment. This chain allows automatic SystemC code generation from high level MPSoC modeling.

The PDF of my PhD thesis